Master’s thesis, in collaboration with Dumarey, Turin, Italy, supervised by a Politecnico di Torino professor together with a senior software manager at Dumarey. June 2026 to present.
Key contributions
- Designing a Type-1 hypervisor at EL2 in Rust for a multi-core Arm Cortex-R52 MCU, targeting partition-based isolation for safety-critical automotive applications
- Designed a static partitioning architecture in which guests are planned to run natively at EL1, request EL2 services through HVC, and be isolated through MPU protection, device ownership, and on-chip firewalls; guest boot and isolation enforcement remain unimplemented
- Generated the Rust peripheral access layer from the SoC’s SVD description using Infineon’s svd2pac, and built a typed model of the SoC’s devices and eDMA engines with a drift-check mode that fails the build when the model and the silicon description diverge
- Validated the ROM-to-EL2 boot path, I-cache, EL2 MPU, exception vectors, and timer register setup on target hardware; implemented RAM ECC initialization, stack setup, and the Rust entry point, with the image passing ELF checks and board validation pending
- Structured the Rust SDK around separate EL1, EL2, and host deployment environments; implemented deployment configuration parsing while static resource allocation, cross-resource validation, and code generation remain in design
- Developed tracebridge, a Rust CLI that automates PowerView startup, flashing, symbol loading, and RTT over the TRACE32 Remote API, with a DAP proxy for debugging in VS Code and RustRover
- Researching fault tolerance for automotive MCU reliability, with single event upsets among the fault classes considered. The next phase will use one core of the SoC together with TRACE32 to inject faults into a running partition, and record how the hypervisor detects them, contains them within that partition, and recovers