Digital design course project on the ALU and multiplier datapath, Turin, Italy.
Key contributions
- Planned the architecture of and implemented the RTL for the processor’s core ALU, supporting add/subtract, logic, and shift operations
- Designed a high-performance multiplier using Radix-4 Booth encoding, halving the number of partial products in a 32-bit multiply and reducing hardware complexity
- Applied a Wallace tree to compress partial products in parallel and Bewick’s algorithm to simplify sign-bit handling, optimizing the adder hierarchy to shorten the combinational critical path
- Built a SystemVerilog simulation environment with testbenches covering signed and unsigned operation, overflow detection, and boundary cases; completed functional verification in ModelSim